module MemWaitGenerator(reset, readEnable, writeEnable, address, counter, WAIT);
input readEnable;
input writeEnable;
input [31:0] address;
input [1:0] counter;
input reset;

output reg WAIT;

wire is_align;

assign is_align = !address[0];

always @(*) begin
	if(!reset) begin
		WAIT <= 0;
	end else if(readEnable || writeEnable) begin
		if(is_align) begin
			if(counter == 0) begin
				WAIT <= 1;
			end else begin
				WAIT <= 0;
			end
		end else begin
			if(counter == 0) begin
				WAIT <= 1;
			end else if(counter == 1) begin
				WAIT <= 1;
			end else begin
				WAIT <= 0;
			end
		end
	end else begin
		WAIT <= 0;
	end
end



endmodule